/IEEE Releases Expansive 2018 Roadmap for Devices and Systems (via Qpute.com)
IEEE Releases Expansive 2018 Roadmap for Devices and Systems

IEEE Releases Expansive 2018 Roadmap for Devices and Systems (via Qpute.com)


IEEE yesterday released the 2018 update to its International Roadmap for Devices and System (IRDS). It’s part history text, part crystal ball, and as IEEE emphasizes, a key reference for the entire electronics value chain. You may remember this report got its start in ~1998 as the International Technology Roadmap for Semiconductors (ITRS) when the focus was squarely on semiconductor technology. It morphed into the IRDS report in 2017 as the decline in Moore’s Law highlighted the rise of many other factors driving computer performance. IEEE and its collaborators responded by expanding the breadth of the report.

As noted in the announcement: “The updated IRDS includes new information on cryogenic electronics and quantum information processing, added benchmarks for applications, and supplemental information and metrics from the More Moore team. In addition, there’s a newly released summary from Beyond CMOS, and updates for emerging devices, outside systems connectivity technology, factory integration (including smart manufacturing and security topics), metrology, and yield enhancement. Market drivers for medical devices and a new automotive market drivers report are also included.”

Let’s say IRDS is more than light summer reading.

On balance, historical information seems most plentiful and many of the projected trends are familiar; nevertheless there’s plenty to dig into. (Check out HPCwire’s coverage of the final ITRS report, Transistors Won’t Shrink Beyond 2021, Says Final ITRS Report) Below is IEEE’s description of the new report:

“The IRDS is a set of predictions that serves as the successor to the ITRS. The intent is to provide a clear outline to simplify academic, manufacturing, supply, and research coordination regarding the development of electronic devices and systems.

“The goals of the roadmap are as follows:

  1. To identify key trends related to devices, systems, and all related technologies by generating a roadmap with a 15-year horizon
  2. To determine generic devices’ and systems’ needs, challenges, potential solutions, and opportunities for innovation
  3. To encourage related activities worldwide through collaborative events, such as related IEEE conferences and roadmap workshops

“The shift and evolution of the roadmap from the ITRS to the IRDS has translated to an expanded focus on systems. Emphasis has been placed on architectures and applications that deviate from the traditional paradigm of device->circuit->logic gate->functional block->system.”

Those are big objectives. Sorting through the report’s high points is beyond the scope of this article. A fair amount of discussion is given to IoT and cloud computing. HPC proper receives a bit less attention. Best to carve out some beach time for reading. It is interesting to note that the 15-year horizon forecast on some of its predictions seem tenuous or directional at best – it’s hard to know much about what 2033 will look like. One example is shown below with explanatory notes at the bottom of the article.

Among IRDS’s extensive contents, it posits a number of Grand Challenges. The lengthy executive summary (~38 pages) provides an overview. Here are a few elements from a Grand Challenge labelled More Moore:

LOGIC DEVICE SCALING
Beyond 2022 a transition from FinFET to gate-all-around (GAA) will start and potentially a transition to vertical nanowires devices will be needed when there will be no room left for the gate length scale down due to the limits of fin width scaling (saturating the Lgate scaling to sustain the electrostatics control) and contact width.

FinFET and lateral GAA devices enable a higher drive at unit footprint if fin pitch can be aggressively scaled while increasing the fin height. This increased drive at unit footprint by scaling the fin pitch comes at a trade-off between fringing capacitance between gate and contact and series resistance. This trend in reducing the number of fins while balancing the drive with increased fin height is defined as fin depopulation strategy, which also simultaneously reduces the standard cell height, therefore the overall chip area.

The most difficult challenge for interconnects is the introduction of new materials that meet the wire conductivity requirements and reduce dielectric permittivity. As for the conductivity, the impact of size effects on interconnect structures must be mitigated. Future effective κ requirements preclude the use of a trench etch stop for dual damascene structures.

DRAM AND 3D NAND FLASH MEMORY
Since the DRAM storage capacitor gets physically smaller with scaling, the EOT (equivalent oxide thickness) must scale down sharply to maintain adequate storage capacitance. To scale the EOT, dielectric materials having high relative dielectric constant (κ) will be needed. Therefore metal-insulator-metal (MIM) capacitors have been adopted using high-κ (ZrO2/Al2O/ZrO2) as the capacitor of 40−30 nm half-pitch DRAM. This material evolution and improvement will continue until 20 nm high- performance (HP) and ultra-high-κ (perovskite κ > 50 ~ 100) materials are released. Also, the physical thickness of the high-κ insulator should be scaled down to fit the minimum feature size. Due to that, capacitor 3D structure will be changed from cylinder to pillar shape.

It’s probably best to think of IRDS as a living document that has grown by accretion, jettisoning little through the years. The result, perhaps necessarily, is the new material seems perhaps a bit thin. Its strength is still on the “semiconductor side” but expansion to systems and more is the right direction.

“The IRDS continues to lead as the go-to reference for researchers, developers and technologists around the world by providing a comprehensive overview of the computer and electronics industry’s trajectory,” said IEEE Fellow Thomas M. Conte, co-chair, IEEE Rebooting Computing Initiative, vice-chair of IRDS, and professor, Georgia Institute of Technology in the official announcement. “The updated IRDS builds upon 16 years of projecting technology needs for the evolving semiconductor and computer industries.”

“The IRDS represents a global effort needed for future computing systems covering many different applications. These worldwide roadmapping activities will allow our community to identify and overcome emerging challenges in this field and to speed-up technology innovation that can drive the development of future markets,” said Francis Balestra, member, Governing Board of the SiNANO Institute, director of research, The French National Center for Scientific Research (CNRS) and vice president of Grenoble Institute of Technology, also quoted in the release.

IRDS partners with regional roadmaps in Europe and Japan. “There are memorandums of understanding (MoUs) with the NanoElectronics Roadmap for Europe: Identification and Dissemination (NEREID, Horizon 2020), of the SiNANO Institute in Europe, and with the Systems and Devices Roadmap committee of Japan (SDRJ) of the Japan Society of Applied Physics,” according to IEEE.

IEEE reports “The updated IRDS can be downloaded by visiting the IRDS home page and joining the IRDS Technical Community. The IRDS is an IEEE Standards Association (IEEE SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative, a program of IEEE Future Directions.”

Link to IEEE release: https://www.businesswire.com/news/home/20190723005052/en/IEEE-Update-International-Roadmap-Devices-Systems-IRDSTM

Link to IRDS page: https://irds.ieee.org

(1)Notes for Table ES2:

ORTC: Logic Notes(1) Based on 0.71x reduction per “Node Range” (“Node” = ~2x Mx).
(2) Based on 0.71x Mx reduction per “Generic Node”, or .5x cell; 2x density; beginning 2013/”G1″/40nm.
(3) Defined as distance between metallurgical source/drain junctions

ORTC: DRAM Notes
(1) The definition of DRAM Half pitch has been changed from this edition. Because of 6F2 DRAM cell, BL pitch is no more critical dimension. pitch= (Cell Area/ Call size factor)^0.5.”
Critical dimension for process development, the Minimum half pitch is also introduced. Currently Active area (long rectangle island shape) half pitch is the critical dimension of 6F2 DRAM.
Calculated half pitch is use the following equation “Calculated half pitch= (Cell Area/ Call size factor)^0.5.” Critical dimension for process development, the Minimum half pitch is also introduced.
Currently Active area (long rectangle island shape) half pitch is the critical dimension of 6F2 DRAM.
(11) Cell size factor = a = (DRAM cell size/F2), where F is the DRAM 1⁄2 pitch. The current values of a are 6 from 2009. And a=4 will be predicted in 2021.

ORTC: NAND Flash Notes
(1) 2D NAND strings consist of closely packed polysilicon control gates (the Word Lines) that separate the source and drain of devices with no internal contact within the cell.
Up to now this uncontacted word line pitch is still the tightest in all technologies.
(6) The number of 3D layers is not a unique function, depending on the cell 1/2 pitch and 3D NAND technology architecture chosen. Lower number of 3D layers generally has lower bit cost,
but other factors such as decoding method, speed performance, easier or harder to get yield, also need to be considered.
The number of 3D layers spans a range since the same density product may be achieved by using smaller 1/2 pitch and fewer layers, or larger 1/2 pitch and more layers.


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