Valens Semiconductor will become a publicly traded company on NYSE as VLN after a merger with PTK Acquisition Corp. Valens provides long-reach, high-speed video and data transmission for the audio-video and automotive industries. The transaction is expected to provide proceeds of approximately $240 million, including up to $115 million in trust from PTK Acquisition Corp. (assuming no redemptions) and $125 million in cash from a fully subscribed PIPE offering led by an established global institutional investor, as well as by Mediatek. “Our chipsets are in high volume production with several leading automotive Tier-1s and are currently on the road in Daimler vehicles,” said Gideon Ben-Zvi, CEO of Valens. “The automotive market presents an immense opportunity that will continue to grow as OEMs introduce new vehicles with far more sensors and displays than ever before.”
Siemens Digital Industries Software’s Questa Verification IP (QVIP) now supports PCIe 6.0. QVIP integrates into all advanced verification environments on any simulator and uses a UVM architecture across all protocols. It is currently available for early adopters.
IAR Systems selected empire ‘ ARM model AArch64 Armv8-A as the simulator technology for the development toolchain IAR Embedded Workbench for Arm. IAR Embedded Workbench with integrated Imperas simulator provides a rapid test and development environment to compile, debug and analyze code without the need for external hardware or boards. The Imperas models cover the envelope of the Arm V8-A Architecture and can be configured to represent any core or implementation.
Cadence digital and custom/analog tools have been optimized and certified for TSMC’s N3 and N4 process technologies, supporting the latest Design Rule Manual (DRM) certification and SPICE correlation. The corresponding N3 and N4 process design kit (PDKs) are available now.
TSMC certified Synopsys’ digital and custom design solutions for the latest TSMC 3nm process technology design-rule manual (DRM) and process design kits. Implementation technologies deployed as part of the 3nm collaboration include support for advanced routing with coloring and via-pillar consideration and flip-flop optimization that aids both performance-focused and low-power designs.
Cadence debuted Clarity 3D Solver Cloud, which provides the ability to scale 3D finite element method (FEM) simulation capacity from 32 cores to thousands of cores using secure connections to Amazon Web Services (AWS). The hybrid approach allows users the option to simulate using local compute resources or cloud simulation resources, with data used by cloud encrypted.
Avery Design Systems updated its PCIe 6.0 and PIPE 6.0 VIP solution, adding support for the latest features and capabilities, including a doubling of data rates compared to PCIe 5.0, to 64 GT/s speeds, the move to PAM4 encoding and FLIT mode, the introduction of low latency FEC, and backwards compatibility with all previous specification versions.
Siemens Digital Industries Software released Simcenter Studio, a web application for exploring system architectures. The software uses AI-based techniques to expand the design space and perform rapid evaluations of system concepts earlier in development. It targets applications in various industries including automotive, aerospace, and heavy machinery.
CacheQ now supports multi-threading acceleration for CPUs with multiple physical cores through its new compiler. It takes single-threaded C code and generates executables that can run on CPUs, leveraging many physical x86 cores with or without hyperthreading, as well as Arm and RISC-V cores. The company says its compiler provides a speedup of more than 486% over single-thread execution on X86 processors with 12 logical cores.
Arm announced several new Armv9 CPUs. Cortex-X2 targets premium smartphones and laptops with 30% performance improvements over current devices. Cortex-A710 is a Armv9 “big” CPU, with a 30% energy efficiency gain and 10% uplift in performance compared to Cortex-A78, targeted for demanding applications on smartphones. Cortex-A510 is a high efficiency “LITTLE” core, delivering 35% performance improvements and over 3x uplift in ML performance compared to its predecessor and targets smartphone, home, and wearable devices. Arm also announced the Mali-G710 as its highest performing GPU targeting premium smartphones and the Chromebook market. The Mali-G610 was released as a sub-premium GPU at a lower price point.
Synopsys launched its DesignWare process, voltage, and temperature (PVT) monitoring and sensing subsystem IP on TSMC’s N3 process technology. The PVT monitoring and sensing subsystem IP has been added to the TSMC9000 Program, TSMC library and IP quality management program and targets AI, data center, HPC, consumer, and 5G markets.
Cadence uncorked third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, AI/ML accelerators, and switch fabric SoCs. The DSP-based, flex-rate multi-rate 112G-LR PAM4 SerDes IP provides 25% power savings, 40% area reduction, and better design margins over the second-generation architecture, the company said.
Cadence also announced PCIe 5.0 IP on TSMC N5. The IP consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022.
CAST released EMSA5-FS, a fault-tolerant embedded RISC-V processor IP core designed to meet the functional safety requirements of automotive, airborne, and other safety-critical applications. Developed by Fraunhofer IPMS, it is a 32-bit, in-order, single-issue, five-stage pipeline processor. It is available for ASICs or FPGAs, and as either a stand-alone processor or pre-integrated in optional subsystems combining a bus fabric with typical peripherals.
PLDA launched its XpressRICH PCIe Controller IP for the PCIe 6.0 specification. The IP implements Forward Error Correction combined with Cyclic Redundancy Check, and also supports the new L0p low power mode, enabling traffic to be transmitted on a reduced set of lanes, reducing power consumption without impacting traffic flow.
The National Energy Research Scientific Computing Center (NERSC) at Lawrence Berkeley National Laboratory (Berkeley Lab) announced the first phase of its next-generation supercomputer, Perlmutter. The system will be used in studies of the climate and the environment, clean energy technologies, semiconductors and microelectronics, and quantum information science. “Perlmutter will provide considerably more computing power than our current supercomputer, Cori, and will introduce several key technologies that will be used in exascale systems in the coming years,” said NERSC Director Sudip Dosanjh. “It will enable a larger range of applications than previous NERSC systems and is the first NERSC supercomputer designed from the very beginning to meet the needs of both simulation and data analysis.”
IBM and the Grainger College of Engineering at the University of Illinois Urbana-Champaign are launching a $200 million, ten year collaboration focusing on hybrid cloud and AI, quantum information science and technology, accelerated materials discovery, and sustainability. “This institute with IBM is a pioneering new model of how we can build academic and researcher collaboration into technology and innovation at unmatched excellence and scale,” said Robert J. Jones, chancellor of the University of Illinois Urbana-Champaign.
Keysight Technologies acquired Quantum Benchmark, a company that provides error diagnostics, error suppression and performance validation software for quantum computing. “Joining forces with Keysight is a strategic and timely opportunity to accelerate the development and delivery of our industry-leading solutions,” said Joseph Emerson, Quantum Benchmark CEO, founder, and Chief Scientist. “Together, we bring the world closer to achieving the break-through applications of quantum computing including the design of energy-efficient materials, the acceleration of drug discovery, the promise of quantum machine learning, and so much more.”
Cambridge Quantum Computing (CQC) said it has found a new algorithm that accelerates quantum Monte Carlo integration, in a pre-print paper. “This new algorithm is a historic advance which expands quantum Monte Carlo integration and will have applications both during and beyond the NISQ era,” said Steven Herbert of CQC. “We are now capable of achieving what was previously only a theoretical quantum speedup. That’s something that none of the existing quantum Monte Carlo integration algorithms can do without substantial overhead that renders current methods unusable.”
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