Mixed-signal PDK for Samsung processes; imaging and video analytics; MIPI D-PHY update; AMD quantum patents.
Tools & IP
Cadence and Samsung Foundry are offering Mixed-Signal OpenAccess-ready process design kit (PDK) technology files that support a range of Samsung process technologies from 28FDS to GAA base 3nm. Enabling access to mixed-signal designs in a common OpenAccess database, the co-design methodology promotes shared responsibilities and collaboration between the analog and digital teams for chip planning, design, implementation, physical verification, and signoff.
SK Telecom licensed Arteris IP’s FlexNoC interconnect IP in its next-generation SAPEON AI SoCs. SK Telecom cited the Arteris local engineering team that was able to assist with configuration.
Xilinx expanded its video and imaging IP portfolio for UltraScale+ and Versal devices. New is HDMI 2.1 and DisplayPort (DP) 1.4 IP, which can be combined with its 8K scaler and mixer IPs for a complete, end-to-end 8K video pipeline. High Dynamic Range (HDR), High Frame Rates and Variable Refresh Rate formats and adaptive sync are also now available for UltraScale+ and Versal. Xilinx also debuted a video analytics software development kit that enables video decoding, pre-processing, AI inference, tracking and post-processing for whole application acceleration on Xilinx platforms.
In addition, Xilinx is launching two new versions of its Versal ACAP products targeting space-grade and defense-grade applications. The space-grade portfolio includes the new Versal AI Core and Versal AI Edge series devices, offering ruggedized, organic ball grid array packaging with extended qualification and burn-in supporting Mil-Std-883 Class B-grade flow and full radiation tolerance. The defense-grade portfolio includes the XQ AI Core, XQ AI Edge, XQ Prime and XQ Premium families. The devices in the portfolio feature ruggedized packaging qualified to Mil-Std-883 Group D standards, tin-lead (Sn/Pb) content with full mitigation of tin-whiskering, and optional M-temp (-55°C to +125°C) support.
QuickLogic uncorked an eFPGA IP generator. Based on the OpenFPGA IP generator, it adds additional features and capabilities specific to implementing and customizing the company’s eFPGA IP solutions, as well as testing and support.
The MIPI Alliance published an update to the MIPI D-PHY specification for connecting megapixel cameras and high-resolution displays to application processors. Version 3.0 doubles the data rate of D-PHY’s standard channel to 9 Gbps, while introducing a Continuous-Time Linear Equalizer (CTLE) on the receiver side of a connection to maintain the interface’s power efficiency for smartphone, IoT, and automotive camera and display applications.
Microchip Technology debuted a 112G PAM4 Ethernet PHY with 1.6T bandwidth. It supports Ethernet rates from 1 to 800 GbE and is an industrial-temperature-grade device with connectivity versatility for design reuse across applications ranging from a retimer, gearbox or reverse gearbox to a hitless 2:1 multiplexor (mux). It targets cloud data centers, 5G, and AI applications.
Infineon launched new current ratings for its EconoDUAL 3 portfolio with TRENCHSTOP IGBT7 chips, expanding to 300 A up to 900 A. The family includes on-state voltage reduction for loss reduction and improved oscillation behavior and the controllability of the IGBT. It targets solar, commercial, construction and agricultural vehicles (CAV), and uninterruptible power supply (UPS) inverters.
AMD recently applied for two patents related to quantum computing, reports The Quantum Daily, which may indicate the processor giant is interested in expanding its efforts in the area. One patent deals with a type of quantum architecture that aims to reduce the number of qubits needed for complex calculations. The other deals with the routing of qubits in a system using bubble nodes.
Codasip has appointed Rupert Baines, formerly CEO of UltraSoC, as the company’s Chief Marketing Officer and a member of the management supervisory board.
Xilinx Adapt, through Sept. 16
AI Hardware Summit, Sept. 13-16
ARC Processor Summit 2021, Sept. 21-22
Ansys IDEAS Digital Forum, Sept. 22-23
For a more complete list of events, click here.
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.
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